From 5aead28d4559bd4acd2a083e249099fa72d5502c Mon Sep 17 00:00:00 2001 From: Jimi Xenidis Date: Mon, 2 Oct 2006 11:07:54 -0400 Subject: [PATCH] [XEN][POWERPC] Add Function to completely flush the I-Cache for a processor Signed-off-by: Jimi Xenidis Signed-off-by: Hollis Blanchard --HG-- extra : transplant_source : %02%F6%E7u%DE%B1%F6%AA%21%15N%E47%125%1A8%96%81%AF --- xen/arch/powerpc/powerpc64/ppc970.c | 27 +++++++++++++++++++++++++++ xen/include/asm-powerpc/cache.h | 1 + 2 files changed, 28 insertions(+) diff --git a/xen/arch/powerpc/powerpc64/ppc970.c b/xen/arch/powerpc/powerpc64/ppc970.c index 04b087513f..11a6711485 100644 --- a/xen/arch/powerpc/powerpc64/ppc970.c +++ b/xen/arch/powerpc/powerpc64/ppc970.c @@ -39,11 +39,38 @@ struct cpu_caches cpu_caches = { .dline_size = 0x80, .log_dline_size = 7, .dlines_per_page = PAGE_SIZE >> 7, + .isize = (64 << 10), /* 64 KiB */ .iline_size = 0x80, .log_iline_size = 7, .ilines_per_page = PAGE_SIZE >> 7, }; + +void cpu_flush_icache(void) +{ + union hid1 hid1; + ulong flags; + ulong ra; + + local_irq_save(flags); + + /* uses special processor mode that forces a real address match */ + hid1.word = mfhid1(); + hid1.bits.en_icbi = 1; + mthid1(hid1.word); + + for (ra = 0; ra < cpu_caches.isize; ra += cpu_caches.iline_size) + icbi(ra); + + sync(); + + hid1.bits.en_icbi = 0; + mthid1(hid1.word); + + local_irq_save(flags); +} + + struct rma_settings { int log; int rmlr_0; diff --git a/xen/include/asm-powerpc/cache.h b/xen/include/asm-powerpc/cache.h index 04f86c64f7..48b8851bdc 100644 --- a/xen/include/asm-powerpc/cache.h +++ b/xen/include/asm-powerpc/cache.h @@ -70,4 +70,5 @@ struct cpu_caches { u32 ilines_per_page; }; extern struct cpu_caches cpu_caches; +extern void cpu_flush_icache(void); #endif -- 2.30.2